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The Intelannounced in catasheet, was the first x87 floating-point coprocessor for the line of microprocessors. The purpose of the was to speed up computations for floating-point arithmetic, such as additionsubtractionmultiplicationdivisionand square root.
It also computed transcendental functions such as exponentiallogarithmic or trigonometric calculations, and besides floating-point it could also operate on large binary and decimal integers. The was an advanced IC for its time, pushing the limits of period manufacturing technology. Initial yields were extremely low. Due to a shortage of chips, IBM did not actually offer the as an option for the PC until it had been on the market for six months.
Development of the led to the IEEE standard for floating-point arithmetic. There were later x87 coprocessors for the not used in PC-compatibles,and SX processors. Starting with thethe later Intel x86 processors did not use a separate floating point coprocessor; floating point functions were provided integrated with the processor.
Intel had previously manufactured the Arithmetic processing unitand the Floating Point Processor. These were designed for use with or similar processors and used an 8-bit data bus. The was initially conceived by Bill Pohlman, the engineering manager at Intel who oversaw the development of the chip. Bill took steps to be sure that the chip could support a yet-to-be-developed math chip.
In Pohlman got the go ahead to design the math chip. Bruce Ravenel was assigned as architect, and John Palmer was hired to be co-architect and mathematician for the project. The two came up with a revolutionary design with 64 bits of mantissa and 16 bits of exponent for the longest format real number, with a stack architecture CPU and 8 bit stack registers, with a computationally rich instruction set.
The design solved a few outstanding known problems in numerical computing and numerical software: Palmer credited William Kahan ‘s writings on floating point as a significant influence on their design.
The design initially met a cool reception in Santa Clara due to its aggressive design. Eventually, the design was assigned to Intel Israel, and Rafi Nave was assigned to lead the implementation of the chip. Palmer, Ravenel and Nave were awarded patents for the design. It worked in tandem with the or and introduced about 60 new instructions. The binary encodings for all instructions begin with the bit patterndecimal 27, the same as the ASCII character ESC although in the higher order bits of a byte; similar instruction prefixes are also sometimes referred to as ” escape codes “.
When the saw the escape code, it would defer to the until it was ready. The first three x’s are the first three bits of the floating point opcode.
Then two m’s, then the latter half three bits of the floating point opcode, followed by three r’s. The m’s and r’s specify the addressing mode information. datasheft
Application programs had to be written to make use of the special floating inte instructions. At run time, software could detect the coprocessor and use it for floating point operations. When detected absent, similar floating point functions had to be calculated in software or the whole coprocessor could be emulated in software for more precise numerical compatibility.
The x87 family does intrl use a directly addressable register set such as the main registers of the x86 processors; instead, the x87 registers form an eight-level deep stack structure  ranging from st0 to st7, where st0 is the top. The x87 instructions operate by pushing, calculating, and popping values on this stack.
Intel – Wikipedia
However, dyadic operations such as FADD, FMUL, FCMP, and so on may either implicitly use the topmost st0 and st1, or it may use st0 together with an explicit memory operand or register; the st0 register may thus be used as an accumulator i. This makes the x87 stack usable as seven freely addressable registers plus an accumulator. This is especially applicable on superscalar x86 processors Pentium of and later where these exchange instructions are optimized down to a zero clock penalty.
When Intel designed theit aimed to make a standard floating-point format for future designs. An important aspect of the from a historical perspective was that it became the basis for the IEEE floating-point standard. daatasheet
(PDF) Datasheet PDF Download – MATH COPROCESSOR
The did not implement the eventual IEEE standard in all its details, as the standard was not finished untilbut the did. The handles infinity values by either affine closure or projective closure selected via the status register.
With affine closure, positive and negative infinities are treated as different values. With projective closure, infinity is treated as an unsigned representation for very small or very large numbers. However, projective closure was dropped from the later formal issue of IEEE The retained projective closure as an option, but the and subsequent floating point processors including the only supported affine closure. The differed from subsequent Intel coprocessors in that it was directly connected to the address and data buses.
The coprocessor handed control back once the execution of the coprocessor instruction was complete.
(PDF) 8087 Datasheet download
daatasheet There was a potential crash problem if the coprocessor instruction failed to decode to one that the coprocessor understood. Intel’s later coprocessors did not connect to the buses in the same way, but were handed the instructions by the main processor. This yielded an execution time penalty, but the potential crash problem was avoided because the main processor would ignore the instruction if the coprocessor refused to accept it.
The was able to detect whether it was connected to an or an by monitoring the data bus during the reset cycle.
In practice, there was the potential for a bus crash if both processors attempted to access either bus simultaneously. All models of the had a 40 pin DIP package and operated on 5 volts, consuming around 2. Unlike later Intel coprocessors, the had to run at the same clock speed as the main processor. Just as the and processors were superseded by later parts, so was the superseded. Other Intel coprocessors were the, and the Starting with thethe later Intel processors did not use a separate floating point coprocessor; virtually all included it on the main processor die, with the significant exception of the SX which was a modified DX with the FPU disabled.
The was in fact a full blown iDX chip with an extra pin. Intel Intel Intel Math Coprocessor. Intel AMD  Cyrix . Die of Intel Intel Math Coprocessor Pinout.
Retrieved 1 December Lemone, page 1 2 3 Shvets, Gennadiy 8 October Intel Math Coprocessor. IntelIBM .